The LA-E801P is a sophisticated multi-layer PCB designed around the Intel Kaby Lake-U processor architecture. The "Rev 2.0" designation is critical; earlier revisions (1.0 or 0.1) often have significant differences in the power sequence and pinout configurations for the embedded controller (EC). Key Components Overview: Integrated Intel Core i3/i5/i7 (Kaby Lake-U).
Disclaimer: Always verify with your specific unit. Modifications are at your own risk. lae801p rev 20 schematic better
Sites like Scribd and Studocu host engineering drawings, though they sometimes require a subscription. The LA-E801P is a sophisticated multi-layer PCB designed
: Technicians report that 3.3V/5V power rail issues are common on this board; Rev 2.0 schematics provide the correct test points and resistance values (e.g., specific 7Ω readings on source sites) to identify shorts. Disclaimer: Always verify with your specific unit
"Always-on" voltages required for the EC (Embedded Controller) to function. +3V_EC: Power for the I/O controller.
Supports Intel Sky Lake-U or Kaby Lake-U processors (BGA 1356P). Memory: Dual DDR4 SODIMM slots.