The internal architecture of is a testament to modern integrated system design. It comprises five primary functional blocks:
| Change | Rationale | |--------|-----------| | ISR → Message Queue (size 128) | Decouples interrupt latency from processing time. | | Use CAN_RxFIFO0 hardware FIFO | Reduces CPU cycles per message. | | Implement CAN_TX_Abort on overload | Guarantees bounded transmission latency. | | Enable recovery logic | Improves robustness to bus errors. | VEC-643